BDD-based implementation of low power 32-bit CRC encoder and decoder

of BDDbased 32-bit CRC encoder and decoder using LFSR methodology, with low power and less area. Generally 32-bit CRC is used in Ethernet frame for fault recognition at the transmitted data. The functional required for LFSR implementation is shift registers, flip flop which works for high frequency and yields less delay and consumes less power, the TSPC flip flop which is suitable for high speed and low power is modified and XOR gate is designed by using BDD (binary decision diagram) based approach which provide 58% improvement in power. Proposed design of 32-bit CRC is implemented in Cadence virtuoso tool using GPDK 180nm CMOS technology, with supply voltage of 1.8V.